-----------------------------------------------
-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/01/2007
-----------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY N_delay IS
	PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
			input			: IN  STD_LOGIC_VECTOR (3 DOWNTO 0);	-- Flop input
      		q	 			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) 	-- Flop output
			);
END N_delay;

ARCHITECTURE str OF N_delay IS
	COMPONENT dflop IS
		PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
				reset			: IN  STD_LOGIC;	-- Resets the flop to 0, active HIGH
				set				: IN  STD_LOGIC;	-- Sets the flop to 1, active HIGH
				input			: IN  STD_LOGIC;	-- Flop input
	      		q	 			: OUT STD_LOGIC 	-- Flop output
				);
	END COMPONENT;
	
	SIGNAL delay_1,delay_2,delay_3,delay_4,delay_5,delay_6,delay_7,delay_8,
			delay_9,delay_10,delay_11,delay_12,delay_13,delay_14,delay_15,
			delay_16,delay_17,delay_18,delay_19,delay_20,delay_21,delay_22,
			delay_23,delay_24,delay_25,delay_26,delay_27,delay_28,delay_29,
			delay_30,delay_31,delay_32,delay_33,delay_34,delay_35,delay_36,
			delay_37,delay_38,delay_39,delay_40,delay_41,delay_42,delay_43,
			delay_44: STD_LOGIC_VECTOR (3 DOWNTO 0);
	
BEGIN
	x_dffx11: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>input(0),q=>delay_1(0));
	x_dffx12: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>input(1),q=>delay_1(1));
	x_dffx13: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>input(2),q=>delay_1(2));
	x_dffx14: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>input(3),q=>delay_1(3));		
	x_dffx21: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_1(0),q=>delay_2(0));
	x_dffx22: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_1(1),q=>delay_2(1));
	x_dffx23: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_1(2),q=>delay_2(2));
	x_dffx24: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_1(3),q=>delay_2(3));		
	x_dffx31: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_2(0),q=>delay_3(0));
	x_dffx32: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_2(1),q=>delay_3(1));
	x_dffx33: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_2(2),q=>delay_3(2));
	x_dffx34: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_2(3),q=>delay_3(3));
	x_dffx41: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_3(0),q=>delay_4(0));
	x_dffx42: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_3(1),q=>delay_4(1));
	x_dffx43: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_3(2),q=>delay_4(2));
	x_dffx44: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_3(3),q=>delay_4(3));
	x_dffx51: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_4(0),q=>delay_5(0));
	x_dffx52: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_4(1),q=>delay_5(1));
	x_dffx53: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_4(2),q=>delay_5(2));
	x_dffx54: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_4(3),q=>delay_5(3));
	x_dffx61: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_5(0),q=>delay_6(0));
	x_dffx62: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_5(1),q=>delay_6(1));
	x_dffx63: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_5(2),q=>delay_6(2));
	x_dffx64: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_5(3),q=>delay_6(3));
	x_dffx71: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_6(0),q=>delay_7(0));
	x_dffx72: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_6(1),q=>delay_7(1));
	x_dffx73: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_6(2),q=>delay_7(2));
	x_dffx74: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_6(3),q=>delay_7(3));
	x_dffx81: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_7(0),q=>delay_8(0));
	x_dffx82: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_7(1),q=>delay_8(1));
	x_dffx83: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_7(2),q=>delay_8(2));
	x_dffx84: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_7(3),q=>delay_8(3));
	x_dffx91: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_8(0),q=>delay_9(0));
	x_dffx92: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_8(1),q=>delay_9(1));
	x_dffx93: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_8(2),q=>delay_9(2));
	x_dffx94: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_8(3),q=>delay_9(3));
	x_dffx101: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_9(0),q=>delay_10(0));
	x_dffx102: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_9(1),q=>delay_10(1));
	x_dffx103: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_9(2),q=>delay_10(2));
	x_dffx104: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_9(3),q=>delay_10(3));
	x_dffx111: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_10(0),q=>delay_11(0));
	x_dffx112: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_10(1),q=>delay_11(1));
	x_dffx113: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_10(2),q=>delay_11(2));
	x_dffx114: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_10(3),q=>delay_11(3));
	x_dffx121: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_11(0),q=>delay_12(0));
	x_dffx122: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_11(1),q=>delay_12(1));
	x_dffx123: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_11(2),q=>delay_12(2));
	x_dffx124: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_11(3),q=>delay_12(3));
	x_dffx131: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_12(0),q=>delay_13(0));
	x_dffx132: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_12(1),q=>delay_13(1));
	x_dffx133: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_12(2),q=>delay_13(2));
	x_dffx134: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_12(3),q=>delay_13(3));
	x_dffx141: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_13(0),q=>delay_14(0));
	x_dffx142: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_13(1),q=>delay_14(1));
	x_dffx143: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_13(2),q=>delay_14(2));
	x_dffx144: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_13(3),q=>delay_14(3));
	x_dffx151: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_14(0),q=>delay_15(0));
	x_dffx152: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_14(1),q=>delay_15(1));
	x_dffx153: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_14(2),q=>delay_15(2));
	x_dffx154: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_14(3),q=>delay_15(3));
	x_dffx161: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_15(0),q=>delay_16(0));
	x_dffx162: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_15(1),q=>delay_16(1));
	x_dffx163: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_15(2),q=>delay_16(2));
	x_dffx164: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_15(3),q=>delay_16(3));
	x_dffx171: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_16(0),q=>delay_17(0));
	x_dffx172: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_16(1),q=>delay_17(1));
	x_dffx173: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_16(2),q=>delay_17(2));
	x_dffx174: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_16(3),q=>delay_17(3));
	x_dffx181: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_17(0),q=>delay_18(0));
	x_dffx182: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_17(1),q=>delay_18(1));
	x_dffx183: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_17(2),q=>delay_18(2));
	x_dffx184: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_17(3),q=>delay_18(3));
	x_dffx191: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_18(0),q=>delay_19(0));
	x_dffx192: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_18(1),q=>delay_19(1));
	x_dffx193: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_18(2),q=>delay_19(2));
	x_dffx194: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_18(3),q=>delay_19(3));
	x_dffx201: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_19(0),q=>delay_20(0));
	x_dffx202: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_19(1),q=>delay_20(1));
	x_dffx203: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_19(2),q=>delay_20(2));
	x_dffx204: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_19(3),q=>delay_20(3));
	x_dffx211: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_20(0),q=>delay_21(0));
	x_dffx212: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_20(1),q=>delay_21(1));
	x_dffx213: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_20(2),q=>delay_21(2));
	x_dffx214: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_20(3),q=>delay_21(3));
	x_dffx221: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_21(0),q=>delay_22(0));
	x_dffx222: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_21(1),q=>delay_22(1));
	x_dffx223: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_21(2),q=>delay_22(2));
	x_dffx224: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_21(3),q=>delay_22(3));
	x_dffx231: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_22(0),q=>delay_23(0));
	x_dffx232: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_22(1),q=>delay_23(1));
	x_dffx233: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_22(2),q=>delay_23(2));
	x_dffx234: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_22(3),q=>delay_23(3));
	x_dffx241: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_23(0),q=>delay_24(0));
	x_dffx242: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_23(1),q=>delay_24(1));
	x_dffx243: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_23(2),q=>delay_24(2));
	x_dffx244: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_23(3),q=>delay_24(3));
	x_dffx251: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_24(0),q=>delay_25(0));
	x_dffx252: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_24(1),q=>delay_25(1));
	x_dffx253: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_24(2),q=>delay_25(2));
	x_dffx254: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_24(3),q=>delay_25(3));
	x_dffx261: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_25(0),q=>delay_26(0));
	x_dffx262: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_25(1),q=>delay_26(1));
	x_dffx263: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_25(2),q=>delay_26(2));
	x_dffx264: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_25(3),q=>delay_26(3));
	x_dffx271: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_26(0),q=>delay_27(0));
	x_dffx272: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_26(1),q=>delay_27(1));
	x_dffx273: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_26(2),q=>delay_27(2));
	x_dffx274: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_26(3),q=>delay_27(3));
	x_dffx281: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_27(0),q=>delay_28(0));
	x_dffx282: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_27(1),q=>delay_28(1));
	x_dffx283: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_27(2),q=>delay_28(2));
	x_dffx284: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_27(3),q=>delay_28(3));
	x_dffx291: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_28(0),q=>delay_29(0));
	x_dffx292: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_28(1),q=>delay_29(1));
	x_dffx293: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_28(2),q=>delay_29(2));
	x_dffx294: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_28(3),q=>delay_29(3));
	x_dffx301: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_29(0),q=>delay_30(0));
	x_dffx302: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_29(1),q=>delay_30(1));
	x_dffx303: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_29(2),q=>delay_30(2));
	x_dffx304: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_29(3),q=>delay_30(3));
	x_dffx311: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_30(0),q=>delay_31(0));
	x_dffx312: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_30(1),q=>delay_31(1));
	x_dffx313: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_30(2),q=>delay_31(2));
	x_dffx314: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_30(3),q=>delay_31(3));
	x_dffx321: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_31(0),q=>delay_32(0));
	x_dffx322: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_31(1),q=>delay_32(1));
	x_dffx323: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_31(2),q=>delay_32(2));
	x_dffx324: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_31(3),q=>delay_32(3));
	x_dffx331: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_32(0),q=>delay_33(0));
	x_dffx332: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_32(1),q=>delay_33(1));
	x_dffx333: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_32(2),q=>delay_33(2));
	x_dffx334: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_32(3),q=>delay_33(3));
	x_dffx341: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_33(0),q=>delay_34(0));
	x_dffx342: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_33(1),q=>delay_34(1));
	x_dffx343: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_33(2),q=>delay_34(2));
	x_dffx344: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_33(3),q=>delay_34(3));
	x_dffx351: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_34(0),q=>delay_35(0));
	x_dffx352: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_34(1),q=>delay_35(1));
	x_dffx353: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_34(2),q=>delay_35(2));
	x_dffx354: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_34(3),q=>delay_35(3));
	x_dffx361: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_35(0),q=>delay_36(0));
	x_dffx362: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_35(1),q=>delay_36(1));
	x_dffx363: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_35(2),q=>delay_36(2));
	x_dffx364: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_35(3),q=>delay_36(3));
	x_dffx371: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_36(0),q=>delay_37(0));
	x_dffx372: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_36(1),q=>delay_37(1));
	x_dffx373: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_36(2),q=>delay_37(2));
	x_dffx374: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_36(3),q=>delay_37(3));
	x_dffx381: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_37(0),q=>delay_38(0));
	x_dffx382: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_37(1),q=>delay_38(1));
	x_dffx383: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_37(2),q=>delay_38(2));
	x_dffx384: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_37(3),q=>delay_38(3));
	x_dffx391: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_38(0),q=>delay_39(0));
	x_dffx392: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_38(1),q=>delay_39(1));
	x_dffx393: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_38(2),q=>delay_39(2));
	x_dffx394: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_38(3),q=>delay_39(3));
	x_dffx401: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_39(0),q=>delay_40(0));
	x_dffx402: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_39(1),q=>delay_40(1));
	x_dffx403: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_39(2),q=>delay_40(2));
	x_dffx404: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_39(3),q=>delay_40(3));
	x_dffx411: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_40(0),q=>q(0));
	x_dffx412: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_40(1),q=>q(1));
	x_dffx413: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_40(2),q=>q(2));
	x_dffx414: dflop PORT MAP (clock=>clock,reset=>'0',set=>'0',input=>delay_40(3),q=>q(3));
END str;
